This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits (IC) may be formed from arrangements of one or more input/output devices, standard devices, memory devices, and/or the like. In one scenario, memory devices may include memory arrays arranged into memory cells and the associated circuitry to write data to the memory cells and read data from the memory cells.
In particular, the memory cells of a memory array, such as a random access memory (RAM) array, may be organized into rows and columns. The logic latches within these individual memory cells may be used to store a data bit that is representative of a logical “1” or “0.” These memory cells may also be interconnected by word-lines (WL) and pairs of complementary bit-lines (BL).
In a further scenario, the memory array may be vulnerable to errors. In particular, these errors may be soft errors, where the state of the data bits stored in the memory array can be changed. In such a scenario, a read operation performed on the memory array may produce incorrect values. As process geometries shrink, and as memory arrays decrease in size, these memory arrays may become increasingly vulnerable to errors. In some scenarios, techniques for detecting such errors may be used.